Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures

ABSTRACT

The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

TECHNICAL FIELD

[0001] The invention pertains to a number of semiconductor structuresand methods for forming such structures, including gate stackstructures, conductive line structures, conductive interconnectstructures, and programmable-read-only-memory devices.

BACKGROUND OF THE INVENTION

[0002] A continuous challenge in semiconductor processing is to improveconductivity and performance of stacked semiconductor structures. Amongthe stacked semiconductor structures commonly utilized are gate stacks,wordlines, programmable-read-only-memory devices such as EPROMs andEEPROMs, and conductive interconnects. Formation of some of these priorart stacked structures is described with reference to FIGS. 1-4. FIGS.1-2 pertain to the formation of a wordline or gate stack structure, andFIGS. 3-4 pertain to the formation of a programmable-read-only memorydevice.

[0003] Referring to FIG. 1, a semiconductor wafer fragment 10 isillustrated at a preliminary processing step of a prior art process forforming a wordline or gate stack. Wafer fragment 10 comprises asemiconductive material substrate 12, and field oxide regions 14 oversubstrate 12. A gate dielectric layer 16, generally comprising silicondioxide, extends between field oxide regions 14. A polysilicon layer 18and a polycide (silicide) layer 20 are formed over field oxide regions14 and gate dielectric layer 16.

[0004] Polysilicon layer 18 typically comprises polysilicon uniformlydoped with a conductivity enhancing dopant (illustrated by stipplingwithin layer 18). Polycide layer 20 comprises a metal silicide, such astungsten silicide, molybdenum silicide, titanium silicide or cobaltsilicide. The formation of polycide layer 20 typically comprisesdepositing a metal over polysilicon layer 18 and reacting the metal withpolysilicon layer 18 to form a metal-silicide. The reacting can comprisethermal processing of the metal layer and polysilicon layer at, forexample, temperatures of from about 600° C. to about 800° C.

[0005] Referring to FIG. 2, layers 16, 18 and 20 are patterned to form aconductive stack, and specifically to form a wordline 24. Source/drainregions 25 are provided proximate wordline 24. Conductive wordline 24comprises a transistor gate electrically connecting source/drain regions25. The final transistor structure can be either a p-channel transistor(PMOS), or an n-channel transistor (NMOS), and can be incorporatedwithin a CMOS construction.

[0006] The speed of devices comprising wordlines and conductive gatesgenerally increases with increasing conductivities of the wordlines andconductive gates. Accordingly, it would be desirable to improve theconductivity of wordlines and transistor gates. A method for improvingthe conductivity of a doped layer is to “activate” the dopant within thelayer. Although the chemistry of dopant activation is not wellunderstood, activation is thought to occur as dopant is dispersed fromgrain boundaries in a polysilicon layer to bulk polysilicon away fromthe grain boundaries. Dopants are typically activated by thermalprocessing.

[0007] Alternative procedures similar to those of FIGS. 1 and 2 can beused to form a conductive polysilicon interconnect. Such interconnectscan comprise a line of polycide over a polysilicon. Accordingly, suchinterconnects are similar to wordline 24, but lack dielectric layer 16.

[0008] The speed of devices comprising conductive interconnects canincrease with increasing conductivities of the conductive interconnects.Accordingly, it would be desirable to improve the conductivity ofconductive interconnects.

[0009] Referring to FIGS. 3-4, a prior art process for forming aprogrammable-read-only memory (PROM) device is illustrated. In theembodiment of FIGS. 3-4, similar numbering to that of the embodiment ofFIGS. 1-2 is utilized, with differences indicated by the suffix “a”, orby different numbers.

[0010] Referring to FIG. 3, a wafer fragment 10 a is illustrated at apreliminary step during formation of a programmable-read-only memorydevice. Wafer fragment 10 a comprises a semiconductive material 12 aover which is formed field oxide regions 14 a and gate dielectric layer16 a. A first polysilicon layer 18 a is formed over regions 14 a anddielectric layer 16 a. A second dielectric layer 26 and a secondpolysilicon layer 28 are formed over first polysilicon layer 18 a, and apolycide layer 30 is formed over second dielectric layer 26.

[0011] Polysilicon layers 18 a and 28 comprise uniformly dopedpolysilicon, typically comprising a dopant concentration of greater than1×10¹⁹ ions/cm³.

[0012] Referring to FIG. 4, layers 16 a, 18 a, 20 a, 26, 28 and 30 arepatterned to form the resulting PROM device 32. Within device 32, thepatterned first polysilicon layer 18 a is typically referred to as afloating gate. The patterned second polysilicon layer 28 and polycidelayer 30 together comprise a conductive line 33.

[0013] The speed of circuits comprising PROM devices can increase withincreasing conductivities of the conductive line and floating gate.Accordingly, it would be desirable to improve the conductivities ofconductive lines and floating gates.

SUMMARY OF THE INVENTION

[0014] The invention encompasses stacked semiconductor devices includinggate stacks, wordlines, PROMs, conductive interconnecting lines, andmethods for forming such structures.

[0015] In one aspect, the invention includes a method of forming aconductive line. A silicide layer is formed against a polysilicon layer.A conductivity-enhancing impurity is provided within the silicide layer.The polysilicon layer and the silicide layer are formed into aconductive line shape.

[0016] In another aspect, the invention includes aprogrammable-read-only-memory device comprising a first dielectric layerover a substrate, a floating gate over the first dielectric layer, asecond dielectric layer over the floating gate, a conductive line overthe second dielectric layer, and a metal-silicide layer over theconductive line. The metal-silicide layer comprises a Group III dopantor a Group V dopant.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0018]FIG. 1 illustrates a semiconductor wafer fragment at preliminarystep of a prior art method for forming a wordline.

[0019]FIG. 2 illustrates the FIG. 1 wafer fragment at a prior art stepsubsequent to that of FIG. 1.

[0020]FIG. 3 illustrates a semiconductor wafer fragment at preliminarystep of a prior art method for forming PROM device.

[0021]FIG. 4 illustrates the FIG. 3 wafer fragment at a prior art stepsubsequent to that of FIG. 3.

[0022]FIG. 5 illustrates a semiconductor wafer fragment at preliminarystep of a first embodiment method of the present invention for forming awordline.

[0023]FIG. 6 illustrates the FIG. 5 wafer fragment at a step subsequentto that of FIG. 5.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0025] A first embodiment of the present invention is described withreference to FIGS. 5 and 6. In describing the first embodiment, likenumerals from the preceding discussion of the prior art are utilizedwhere appropriate, with differences being indicated by the suffix “b” orwith different numerals.

[0026] Referring to FIG. 5, a semiconductor wafer fragment 10 b isillustrated at a preliminary processing step. Wafer fragment 10 bcomprises a semiconductive material substrate 12 b, such as, forexample, monocrystalline silicon. Field isolation regions 14 b and agate dielectric layer 16 b are formed over semiconductive material 12 b.Field isolation regions 14 b and gate dielectric layer 16 b comprise aninsulative material, such as, for example, silicon dioxide.

[0027] A conductive layer 18 b and a polycide layer 20 b are formed overfield isolation regions 14 b and gate dielectric layer 16 b. Conductivelayer 18 b preferably comprises polysilicon doped to a concentration ofgreater than 1×10¹⁹ atoms/cm³ with a conductivity enhancing dopant.Polycide layer 20 b is against conductive layer 18 b and comprises ametal silicide doped with conductivity enhancing dopant (the dopantbeing indicated by stippling). Preferably, polycide layer 20 b is dopedto a concentration of greater than 1×10¹⁸ atom/cm³ with the conductivityenhancing dopant.

[0028] Polycide layer 20 b can comprise, for example, a metal selectedfrom the group consisting of tungsten, tantalum, titanium, molybdenumand cobalt. Polycide layer 20 b can be formed by the prior art method ofdepositing a metal over polysilicon layer 18 b and reacting the metalwith polysilicon layer 18 b at temperatures of from about 600° C. toabout 800° C. to form silicide layer 20 b. Alternatively, andpreferably, the thermal processing to form polycide layer 20 bencompasses rapid thermal processing (RTP). In the context of thisdocument, RTP refers to a process wherein a temperature is ramped atgreater than about 7° C./second. Preferably, the RTP temperature isramped to exceed 850° C. and is maintained above 850° C. for at least 10seconds. Such RTP can activate dopant within polycide layer 20 b toincrease the conductivity of doped polycide layer 20 b.

[0029] The RTP preferably occurs while exposing silicide layer 20 b toan oxygen-comprising atmosphere, such as, for example, an atmospherecomprising at least one compound selected from the group consisting ofO₂, O₃, N₂O and NO. Under such preferred conditions, a silicon dioxidelayer 35 can be formed over polycide layer 20 b. Silicon dioxide layer35 can impede or prevent dopant diffusion outwardly from layer 20 b andthereby advantageously retain dopant within layer 20 b. It is noted thatwhile the RTP preferably occurs while exposing layer 20 b to anoxidizing atmosphere, the RTP will generally also activate dopant withinlayer 20 b if conducted while exposing layer 20 b to a non-oxidizingatmosphere.

[0030] Wafer 10 b differs from wafer 10 of the prior art (shown in FIGS.1 and 2) in that polycide layer 20 b is doped with aconductivity-enhancing impurity, whereas the prior art polycide 20(shown in FIGS. 1 and 2) is not doped. As indicated above, theconductivity-enhancing dopant is preferably provided to a concentrationof greater than 1×10 ¹⁸ atom/cm³. Suitable conductivity enhancingdopants can comprise, for example, Group III or Group V dopants, such asdopants comprising boron, phosphorous or arsenic. Methods for dopingsilicide layer 20 b include, for example, implanting dopant into thelayer after formation/deposition of the layer, in situ doping of thelayer during either chemical vapor deposition (CVD) or sputterdeposition, and out-diffusion from a doped polysilicon layer 18 bbeneath silicide layer 20 b.

[0031] An example CVD process for forming a polycide layer 20 bcomprising tungsten silicide doped with phosphorus (WSi_(x)P_(y))comprises utilization of WF₆, SiH₄ and PH₃ as precursor materials in aCVD reactor. Alternatively, dichlorosilane can be substituted for SiH₄.Also, alternative dopant hydrides can be substituted for PH₃ to form apolycide doped with an alternative dopant. Such alternative metalhydrides can include, for example, AsH₃ or diborane. Also, other organicprecursors comprising Group III or Group V dopants can utilized asalternative sources of dopant.

[0032] An example sputter deposition process comprises utilization of atarget comprising a mixture of a source of metal, a source of siliconand a source of conductivity-enhancing impurity. The target is sputteredto form a silicide layer 20 b comprising the conductivity-enhancingimpurity and the metal.

[0033] Referring to FIG. 6, layers 16 b, 18 b, 20 b, and 35 arepatterned to form a conductive line 24 b. Source/drain regions 25 b areformed within substrate 12 b such that conductive line 24 b comprises astacked transistor gate structure which electrically connectssource/drain regions 25 b. The resulting transistor structure can be aPMOS transistor or NMOS transistor, and can be incorporated into a CMOSstructure.

[0034] Conductive line 24 b differs from conductive line 24 (shown inFIG. 2) in that line 24 b comprises a silicide layer 20 b doped withconductivity-enhancing impurity. Such doping of layer 20 b can lower theresistance of layer 20 b relative to that of layer 20 (shown in FIG. 1)and thereby improve the performance of conductive line 24 b relative tothat of conductive line 24 (shown in FIG. 2). The above-discussed RTPcan further improve the conductivity of layer 20 b by activating dopantwithin layer 20 b.

[0035] Although layer 20 b is doped prior to patterning of layer 20 b toform wordline 24 b in the shown method, in alternative embodiments layer20 b can be doped after such patterning. As an example method ofaccomplishing such alternative embodiments, layer 20 b could be doped byion implanting a conductivity enhancing dopant into layer 20 b afterpatterning of layer 20 b to form wordline 24 b. As another examplemethod, layer 20 b can be doped by out-diffusion from conductively dopedlayer 18 b by thermal treatment of wordline 24 b. The doped silicide ofthe present invention can be incorporated into numerous circuit devicestructures, including, for example, programmable-read-only-devices suchas EPROMS and EEPROMS.

[0036] To aid in interpretation of the claims that follow, the term“semiconductive substrate” is defined to mean any constructioncomprising semiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove.

[0037] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A method of forming a conductive line comprising the following steps: forming a polysilicon layer; forming a silicide layer against the polysilicon layer; providing a conductivity-enhancing impurity within the silicide layer; and providing the polysilicon layer and the silicide layer into a conductive line shape.
 2. The method of claim 1 wherein the silicide comprises a metal selected from the group consisting of tungsten, titanium, molybdenum and cobalt.
 3. The method of claim 1 wherein the steps of forming the silicide layer and providing the conductivity-enhancing dopant therein together comprise: depositing a metal together with the conductivity-enhancing impurity on the polysilicon layer; and reacting the metal with the polysilicon to form the silicide layer having the conductivity-enhancing impurity therein.
 4. The method of claim 1 wherein, the step of forming the silicide layer comprises chemical vapor depositing silicide on the polysilicon layer; and the step of providing the conductivity enhancing impurity comprises chemical vapor depositing the conductivity-enhancing impurity in situ with the chemical vapor depositing of the silicide.
 5. The method of claim 1 wherein, the step of forming the silicide layer comprises chemical vapor depositing a tungsten-comprising silicide on the polysilicon; the step of providing the conductivity-enhancing impurity comprises chemical vapor depositing the conductivity-enhancing impurity in situ with the chemical vapor depositing of the tungsten-comprising silicide; and the conductivity-enhancing impurity comprises a group III or a group V element.
 6. The method of claim 5 wherein the step of chemical vapor depositing the conductivity-enhancing impurity comprises utilizing a precursor compound selected from the group consisting of PH₃, AsH₃, and diborane.
 7. The method of claim 1 wherein the conductivity-enhancing impurity is provided to a concentration of at least about 1×10¹⁸ ions/cm³ within the silicide layer.
 8. The method of claim 1 wherein the step of forming the silicide layer and the step of doping the silicide layer together comprise: providing a target comprising a metal, silicon and the conductivity-enhancing impurity; and sputtering of the target to form the silicide layer and the conductivity-enhancing impurity within the silicide layer, the silicide layer comprising the metal.
 9. The method of claim 1 wherein the step of providing the conductivity-enhancing impurity comprises: ion implanting the conductivity-enhancing impurity into the silicide layer after forming the silicide layer.
 10. The method of claim 1 wherein the polysilicon layer is doped with the conductivity-enhancing impurity, and wherein the step of providing the conductivity-enhancing impurity comprises: out-diffusing the conductivity-enhancing impurity from the doped polysilicon layer into the silicide layer.
 11. The method of claim 1 wherein the step of providing the conductivity-enhancing impurity comprises: gas phase chemical doping of the silicide layer.
 12. The method of claim 1 wherein the conductive line is a wordline.
 13. A method of lowering the resistivity of a metal-silicide layer comprising doping the metal-silicide layer with a Group III dopant or a Group V dopant.
 14. The method of claim 13 wherein the dopant is provided to a concentration within the metal-silicide layer of at least about 1×10¹⁸ ions/cm³.
 15. A method of forming a conductive line comprising the following steps: forming a polysilicon layer; forming a silicide layer against the layer of polysilicon; providing a conductivity-enhancing impurity within the silicide layer; and after providing the conductivity-enhancing impurity within the silicide layer, subjecting the silicide layer to a processing step of over 850° C. for at least 10 seconds.
 16. The method of claim 15 wherein the forming the silicide layer comprises depositing a metal layer over the polysilicon and reacting the metal layer with the polysilicon, and wherein the conductivity-enhancing impurity is provided within the metal layer prior to the reacting the metal layer with the polysilicon.
 17. The method of claim 15 wherein the forming the silicide layer comprises depositing a metal layer over the polysilicon and reacting the metal layer with the polysilicon, and wherein the conductivity-enhancing impurity is provided within the metal layer after the reacting the metal layer with the polysilicon.
 18. The method of claim 15 wherein the conductivity-enhancing impurity is implanted into the silicide layer.
 19. The method of claim 15 wherein the conductivity-enhancing impurity is provided to a concentration within the silicide layer of at least about 1×10¹⁸ ions/cm³.
 20. A method of forming a conductive line comprising the following steps: forming a polysilicon layer; forming a silicide layer against the layer of polysilicon; providing a conductivity-enhancing impurity within the silicide layer; and subjecting the silicide layer to a processing step of over 850° C. for at least 10 seconds while exposing the silicide layer to an oxygen-comprising atmosphere.
 21. A conductive line comprising: a polysilicon layer; and a metal-silicide layer against the layer of polysilicon, the metal-silicide layer comprising a Group III dopant or a Group V dopant.
 22. The conductive line of claim 21 wherein the metal-silicide layer comprises a concentration of the dopant of at least about 1×10¹⁸ ions/cm³.
 23. A metal-silicide layer comprising a Group III dopant or a Group V dopant.
 24. The metal-silicide of claim 23 comprising a concentration of the dopant of at least about 1×10¹⁸ ions/cm³.
 25. A programmable-read-only-memory device comprising: a first dielectric layer over a substrate; a floating gate over the first dielectric layer; a second dielectric layer over the floating gate; a conductive line over the second dielectric layer; and a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.
 26. The programmable-read-only-memory device of claim 25 wherein the device is an EPROM.
 27. The programmable-read-only-memory device of claim 25 wherein the device is an EEPROM.
 28. The programmable-read-only-memory device of claim 25 wherein the metal-silicide layer comprises a concentration of the dopant of at least about 1×10¹⁸ ions/cm³. 